Conventionally, in producing a semiconductor integrated circuit on a semi-insulating compound semiconductor substrate such as GaAs, active elements and passive elements which constitute an integrated circuit are produced directly on the semi-insulating compound semiconductor substrate.
FIG. 3 shows such a conventional integrated circuit utilizing a semi-insulating compound semiconductor substrate. In FIG. 3, a MESFET 3 as an active element and a resistor 4 as a passive element are formed by ion implantation directly in a semi-insulating GaAs substrate 1. Reference numerals 5, 6, and 7 designate a gate electrode, a source electrode, and a drain electrode, respectively. Reference numeral 9 designates an n type layer and reference numeral 10 designates an n.sup.+ type layer, both produced in the GaAs substrate 1. The MESFET 3 comprises these layers and electrodes. Reference numeral 8 designates an ohmic electrode and reference numeral 11 designates an n type resistor layer which is produced in the GaAs substrate 1. The resistor 4 comprises this layer 11 and these electrodes 8.
In such a conventional integrated circuit structure, an advantage of employing the semi-insulating GaAs substrate 1 is effectively utilized, that is, there is no need to pay special attention to electrical isolation between elements because the semi-insulating GaAs substrate automatically isolates the elements, simplifying element structure and circuit construction.
In such a conventional integrated circuit where the insulating property of the substate 1 is used to isolate elements, reduction of the separation between elements or between element constituting portions to increase the degree of integration increases the leakage current inside the GaAs substrate 1, adversely affecting element and circuit characteristics.
FIG. 4 shows a device in which the leakage current of an FET produced in a p type semi-insulating GaAs substrate is suppressed. This device is disclosed in Japanese Published Patent Application No. 62-71278.
In FIG. 4, the same reference numerals designate the same or corresponding elements as those shown in FIG. 3.
A GaAs layer 2 including p type dopants has a thickness in substrate 1 that is deeper than the depth of the integrated circuit elements subsequently formed in it. Active elements, for example, a MESFET 3 which has an n type layer 9 and operates with n type carriers as majority carriers, are produced on the p type GaAs layer 2.
In this device, the bulk is effectively completely constituted by the p type layer 2. The potential of the p type layer 2 is V.sub.psub .ltoreq.0, so that the potential barrier between n and p type layers and that between n.sup.+ and p type layers is increased and the substrate leakage current is reduced. At the same time, the inter-element n.sup.+ -p-n.sup.+ type parasitic transistor is turned off and inter-element isolation is realized. Thus, the substrate leakage current is reduced by voltage control of the p type substrate, as described in the patent publication.
In the device of FIG. 4, however, it is doubtful that the element isolation would really be completely successful because the semi-insulating property of the GaAs substrate is not utilized for element separation. Parasitic capacitances are likely to be produced at many places. Accordingly, the speed of operation is likely to be reduced.
FIG. 5 shows a device in which, in order to solve the above-described problem, a p type buried layer is selectively produced on the surface of a semi-insulating GaAs substrate. That device is disclosed in FIG. 5 of Japanese Published Patent Application No. 62-214672. In FIG. 5, reference numeral 21 designates a semi-insulating GaAs substrate, reference numeral 22 designates an n type active layer, reference numeral 23 designates source and drain electrodes, reference numeral 24 designates a gate electrode, reference numerals 25 and 26 designate n type high dopant concentration (n.sup.+ type) drain and source layers (herein either may be a drain layer), and reference numeral 27 designates a p type buried layer.
In this device, since the p type layer 27 is produced selectively in the semi-insulating GaAs substrate 21 and is surrounded by the GaAs substrate 21, element isolation is completely achieved and the operation speed is not reduced.
The device of FIG. 5, however, is susceptible to soft error. The cause of soft error according to the patent publication is the generation of electron-hole pairs along the paths of incident alpha rays. In the thermal equilibrium, the number of generated holes and electrons are equal to each other. However, since the p type buried layer 27 is completely depleted, an electric field exists in the substrate directly below the channel layer. The generated holes drift toward the source side and the electrons toward the drain side. Since the mobility of electrons is higher than that of holes by more than ten times, where the mobility determines the drifting speed, holes remain in the substrate even after electrons are all collected at the drain. Accordingly, the potential at one side of the substrate is lowered and electrons are injected from the source to the substrate, producing a current flow through a current path other than the original current path. This current is observed because of a carrier amplification effect which occurs upon the incidence of alpha rays.
FIGS. 6 and 7 show devices which are disclosed in FIGS. 1 and 2 of Japanese Published Patent Application No. 62-214672, respectively. In FIG. 6, the same reference numerals designate the same or corresponding elements as those shown in FIG. 5. Reference numeral 28 designates a p type high dopant concentration (p.sup.+ type) buried layer and reference numeral 27 designates a p type low dopant concentration (p.sup.- type) layer. In FIG. 7, reference numeral 29 designates a control electrode.
In the devices shown in FIGS. 6 and 7, soft errors are said to be suppressed by the following mechanism. When only holes remain in the substrate as described above, it is possible to prevent the lowering of the potential at one side of the substrate due to holes in the neutral region (non-depleted layer) in the p.sup.+ type buried layer 28 and to prevent soft error. In the structure of FIG. 7, a control electrode 29 is provided in contact with a p.sup.+ type buried layer 28 to control the voltage of the p.sup.+ type buried layer 28. The remaining holes all flow out through the control electrode 29, improving the prevention of soft errors.
Thus, in the device of FIGS. 6 and 7, a p.sup.+ type buried layer 28 is provided to increase the potential barrier between the n channel layer 20 and the p.sup.+ type buried layer, thereby enhancing the anti-soft suppression error property. Further, a p.sup.- type layer 27 is provided between the n channel layer and the p.sup.+ type buried layer to lower the gate parasitic capacitance which otherwise reduces the operation speed.
In the devices shown in FIGS. 6 and 7, however, there are limitations in the improvement in the anti-soft error property because the drain layer is not completely surrounded by a p.sup.- type layer 27 and the p.sup.+ type layer 28. In Japanese Published Patent Application No. 62-214672, it is not explicitly stated that the layer 25 is a drain layer. Electrons generated in the region of the GaAs substrate 21 due to incidence of alpha rays may flow into the n.sup.+ type drain layer 26 as shown in FIG. 7(b).